Hermetic and Vacuum Wafer Level Packaging (WLP)

Wafer-level packaging (WLP), once considered a feature in MEMS design and manufacturing has now become a requirement.

More than 80% of programs at IMT implement WLP with some projects requiring as many 6 wafers for integration and miniaturization. It is a key technology competency at IMT.

With technology requirements converging, it is now commonplace to integrate what were once disparate process technologies and modules into single devices at the wafer level.

Details

IMT implements materials such as silicon, glass, quartz, metals, and others to realize these devices, often mixing and matching other technology modules, such as IMT’s through silicon vias (TSVs), to simplify routing and to signals to the outside world.

IMT routinely achieves over 99% hermeticity with its wafer level packages, including sub-mTorr vacuum WLP for applications that require high vacuum packaging.

IMT utilizes wafer-level packaging technology in several production programs that requires 4 and 5 wafers stacked together.

IMT differentiates itself by blazing the trail in complex integration of process and technologies though wafer-level packaging.